In the manufacture of semiconductor devices, features are lithographically defined, in part, by exposing patterned photoresist to light at a certain wavelength and etched. Two known techniques used in a patterned etch are inorganic anti-reflective coating (ARC) hard masking and spin-on organic bottom anti-reflective coating (BARC). Inorganic ARC hard masking patterning schemes pose difficulties for some application because the amount of photoresist required to protect the hard mask during the hard mask etch place a lower limit on photoresist thickness. This limit can prevent the use of the thinner photoresist films that give better resolution. Although the spin-on BARC is relatively easier to apply, it is typically so similar to photoresist in its chemical composition and thus etch properties that it also requires a thick photoresist. To circumvent these issues, the use of amorphous carbon thin films underlying a tetra-ethyl-ortho-silicate (TEOS) layer is proposed.
Also, as the technology becomes more advanced, the feature size is reduced to allow more devices to be placed on an integrated circuit (IC) die. However, reducing the feature size in, for example, a gate layer mask, will cause defects in the photoresist and underlying layers to cause pattern defects in the surface of the integrated circuit that render the integrated circuit non-functional.
Therefore, what is needed is a method for reducing pattern defects in the manufacture of advanced semiconductor devices.
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